.MODULE         Double_Precision_Divide;

{
        Double-Precision Division
                Z = X / Y

        Calling Parameters
                AY0 = LSW of Y
                AY1 = MSW of Y
                SR1 = MSW of X
                SR0 = Next Significant Word of X
                MR1 = Next Significant Word of X
                MR0 = LSW of X
                SE = -15

        Return Values
                MR1 = MSW of Z
                MR0 = LSW of Z

        Altered Registers
                AF,AR,AX1,AX0,SI,SR,MR

        Computation Time
                485 cycles (maximum)

}

.ENTRY  ddivs;
.ENTRY  ddivq;

ddivs:  AF=PASS SR1;
        SI=SR0, AR=SR1 XOR AY1;     {Exclusive or sign bits}
        AX1=AR;
        SR=LSHIFT MR0 BY 1(LO);     {Shift dividend up one bit}
        SR=SR OR LSHIFT MR1 BY 1(HI);
        SR=SR OR LSHIFT AR(LO);     {Shift in quotient bit}
        AR=PASS AF, MR0=SR0;
        MR1=SR1, SR=LSHIFT MR1(LO);
        SR=SR OR LSHIFT SI BY 1(LO);
        SR=SR OR LSHIFT AR BY 1(HI);
        CNTR=31;
        JUMP ddiv;
ddivq:  CNTR=32;
        AX1=0;
ddiv:   AX0=AY1;
        DO ddivu UNTIL CE;
                AR=ABS AX1;        
                IF POS JUMP aqz;   {Is quotient bit set?}
aqo:            AR=SR0+AY0;        {Yes, add divisor to partial remainder}
                SI=AR, AF=SR1+AY1+C;
                JUMP ddivi;
aqz:            AR=SR0-AY0;        {No, subtract divisor from partial remainder}
                SI=AR, AF=SR1-AY1+C-1;
ddivi:          SR=LSHIFT MR0 BY 1(LO); {Shift dividend one bit}
                SR=SR OR LSHIFT MR1 BY 1(HI);
                AR=AX0 XOR AF;     {Compute quotient bit}
                AX1=AR;            {Save quotient bit}
                AR=NOT AX1;
                SR=SR OR LSHIFT AR(LO); {Shift in new bit}
                MR0=SR0, AR=PASS AF;
                MR1=SR1, SR=LSHIFT MR1(LO);
                SR=SR OR LSHIFT SI BY 1(LO);
ddivu:          SR=SR OR LSHIFT AR BY 1(HI);
                RTS;

.ENDMOD;

//本代码Blackfin示例