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AD7888是8通道,12位,125kSPS低功耗AD转换器,结构如图所示:

引脚如图所示:

引脚功能如表所示:
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Pin No.
|
Mnemonic |
Function
|
|
1 |
CS |
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7888 and also frames the serial data transfer. |
|
2 |
REF |
IN/REF OUT Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888. Alternatively, the internal reference can be disabled and an external reference applied to this input. The voltage range for the external reference is from 1.2 V to VDD. |
|
3 |
VDD |
Power Supply Input. The VDD range for the AD7888 is from 2.7 V to 5.25 V. |
|
4,13 |
AGND |
Analog Ground. Ground reference point for all circuitry on the AD7888. All analog input signals and any external reference signals should be referred to this AGND voltage. Both of these pins should connect to the AGND plane of a system. |
|
5-12 |
AIN1¨CAIN8 |
Analog Input 1 through Analog Input 8. Eight single-ended analog input channels that are multiplexed into the on-chip track/hold. The analog input channel to be converted is selected by using the ADD0 through ADD2 bits of the Control Register. The input range for all input channels is 0 to VREF. Any unused input channels should be connected to AGND to avoid noise pickup. |
|
14 |
DIN |
Data In. Logic Input. Data to be written to the AD7888’s Control Register is provided on this input and is clocked into the register on the rising edge of SCLK (see Control Register section). |
|
15 |
DOUT |
Data Out. Logic Output. The conversion result from the AD7888 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists
of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. |
|
16 |
SCLK |
Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing serial data to the Control Register. This clock input is also used as the clock source for the AD7888’sconversion process. |
输入数据格式:
前八位为:

其中ADD2-ADD0用来选择下一次传送的通道。REF=0表示使用AD7888内部的参考电压。PM1,PM0=0表示使用普通功耗模式。
后8位无效。
时序图:

典型电路
PF1
MOSI
MISO
SCLK
BF533
根据AD7888的特点和两者连接情况,进行如下初始化
// Set baud rate SCK = HCLK/(2*SPIBAUD) SCK = 2MHz
*pSPI_BAUD = 24; //SCLK_SPEED/9216000;
// configure spi port
// SPI Master, enable, MSB first, 16-bit data, low active, SPI write start, software select slave
*pSPI_CTL = MSTR | SPE | GM | SIZE|CPOL|0x01|CPHA;
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