| 主题：直接数字频率合成应用的频率规划 |
| 在线问答： |
| [问：kedadizhi] |
DDS通过标准正弦波查表来生成波形，请问正弦波的表可以通过下载来改变吗，这样可以用计算机软件来编程生成多频率合成的波形表，方式会更灵活一些。 |
| [答：Dan] |
No. Because the look-up table is part of algorithm and is the proprety of ADI and can"t be shared |
[2005-3-4 10:48:38] |
| [问：vvvzhzhh] |
对于数据采集系统来说，如何具有内置PLL芯片的选择？对抗混叠滤波设计有那些方便之处？
|
| [答：Jing] |
If you want to get better output performance,you had better select external high performance PLL with expensive VCO. You should confirm your output frequency and your clock frequency. Then the output frequency will less than 40% of Fclock * PLL . For anti alias ,the PLL will result in 20LOGX (x for PLL multipler). Then you can increase the frequency of the input clock. |
[2005-3-4 10:48:42] |
| [问：dsp_zfg] |
请问AD6644的采样时钟，用AD9954好，还是用AD9854好，或是用什么芯片更好？ |
| [答：Richard] |
AD9954的性能比AD9854要好，但是对于AD6644这样高速的ADC，并不建议用DDS，最好是采用ADI 的 PLL 作为时钟源
|
[2005-3-4 10:49:57] |
| [问：dsp_zfg] |
请问怎样才能获得最佳的AD采样时钟？ |
| [答：Forest] |
一般不建议采用DDS的产品来产生用于AD采样的时钟，因为AD的采样时钟要求很高的精度。 |
[2005-3-4 10:49:58] |
| [问：leo1981cn] |
请问现在幅度分辨率最高的DDS能达到多少位？有没有18位的？ |
| [答：Dan] |
No. The highest one is 14bit and we are trying to push it to 16bit (this is the DAC resolution) |
[2005-3-4 10:50:46] |
| [问：chinawml] |
请问：DDS输出的频谱分量如何计算？或者说，如何知道DDS合成波形的频谱是怎样分布的？ |
| [答：Yiming] |
In the DDS output, there are at least 5 kinds of spurs as the presentation discribed: reference clock, phase truncation, phase-to-amplitude spur, DAC non-linearity, and digital feedthrough. The computer methods are listed in this presentation. |
[2005-3-4 10:51:53] |
| [问：mazee] |
请问用软件方法能否实现DDS（配合DA或者逆变电路）？ |
| [答：Richard] |
从原理上来说， 采用DAC， 和软件查表，加上一些滤波的办法也是可以实现DDS,但是如果要保证较好的性能 （ 如相噪）等，建议用ADI集成的DDS |
[2005-3-4 10:52:47] |
| [问：kuangshunlan] |
请教直接数字频率合成和DAC在应用上的不同和相同（如果有相同之处）之处。 |
| [答：Jing] |
Generally, there is a DAC in DDS . DDS is a digital sine wave technology. You can use DDS (tune word)to adjust the output frequency and phase . We often use DAC in some control field . While we use DDS as wave generator, PLL clock and synthesizer. |
[2005-3-4 10:53:15] |
| [问：SONGCAIJUN] |
AD9854在Single-Ended Reference Clock Input模式下的输入REFCLK还需要有1.6V左右的直流么? |
| [答：Richard] |
参考时钟单端模式输入下，需要高电平至少需要2.3V |
[2005-3-4 10:55:03] |
| [问：david8051] |
目前DDS是否有同時輸出sin與cos兩組信號的功能.也就是有互差90的信號. |
| [答：Jing] |
You can use two chip DDS to get the output or you can use out quadrature DDS (AD9854) to realise the output. |
[2005-3-4 10:55:38] |
| [问：liuyaxin] |
1.目前限制DDS技术发展的瓶颈是什么
2.实现连续频率可调，最好的方法是改变频率控制字，还是时钟源？ |
| [答：Pascal] |
The bottleneck is the fact that DDS requires a clock frequency which is more than twice the frequency of the desired output signal (except if an image in a higher Nyquist zone is acceptable). THis means that at this time, IC DDS has a maximum clock rate of 1GHz. However, this will be rising in the future.
To create swept FM, the clock frequency is held constant, and the DDS tuning word is incremented.
|
[2005-3-4 10:58:05] |
| [问：wyl289] |
DDS的差分输出和单端输出对性能有什么影响？
|
| [答：Jing] |
differential output is better than single end output. Because diffenertial output can get better common mode rejection ratio performance. |
[2005-3-4 10:58:56] |
| [问：pjf] |
目前采用DDS技术，是否能够产生信号带宽1GHz，中心频率在500MHz的线性调频信号，即超宽带信号产生技术中DDS的应用前景如何。
谢谢 |
| [答：David] |
No, our fastest DDS samples at 1GHz. This provides approximately 40% of bandwidth or 400Mhz. Above 40% it is to hard to filter out the image frequency.
DDS is not yet suitable for UWB applications directly. |
[2005-3-4 10:59:07] |
| [问：kedadizhi] |
DDS芯片扫频时的噪声情况与产生单频时的情况相同吗？工作在FSK模式呢 |
| [答：Forest] |
扫频时的噪声与产生单频的时的噪声不一样，相对要差一点。工作在FSK由于是固定的两个频率输出，所以和产生单频的情况相同。 |
[2005-3-4 10:59:14] |
| [问：insighter] |
AD公司是否有频率从10MHz 到 1.25GHz 的 Fractional-N SYNTHESIZER，AD2812是不是依据参考时钟只能提供几个固定的频率点？
|
| [答：Yiming] |
(1)Yes, ADI can provide up to 3GHz fractional PLL products. (2) AD2812? a wrong part number? I can not find such frequency synthesizer. |
[2005-3-4 10:59:48] |
| [问：goodman302] |
请问：DDS杂散的主要杂散源的抑止方法都有哪些？ |
| [答：Fountain] |
1.Choose a low noise reference clock, and prefer external clock, not use internal PLL for high performance application
2.design external low pass filter
3.PCB problem, please be cautious the board digital clock coupling
And also some other ticks you can find in the presentation, we also have a DDS tutorial, you can download it from our website |
[2005-3-4 11:00:03] |
| [问：jida_song] |
您能不能介绍几种应用电路（无线通信） |
| [答：Jing] |
Yes ,we can. But I can"t clearify it clearly here. If you are interested in it. Please send an e-mail to me at Jing.zhang@analg.com. I will give you some application circuit |
[2005-3-4 11:01:02] |
| [问：lijin_as] |
请给出那篇文章的链接地址
|
| [答：Fountain] |
you can send us a email to china.support@analog.com, we can send to you immediately |
[2005-3-4 11:01:55] |
| [问：hamber007] |
DDS中DAC的精度对DDS的性能影响有多大?是否是频率越高,DAC的分辨率要高? |
| [答：Richard] |
DAC的精度会影响到输出的SNR,从而影响到DDS输出的噪声。如果你对DDS的相噪有更高的要求，就要使用更高分辨率的DDS |
[2005-3-4 11:03:02] |
| [问：hoosee] |
在DDS设计中，如何用硬件的方法减少频域中杂散的问题？ |
| [答：Yiming] |
1. use a better bandpass filter to select your expected frequency.
2. Carefully layout your PCB.
3. Good reference, with higher frequency.
Hope this can help you. |
[2005-3-4 11:05:07] |
| [问：casaki] |
请问DDS频率合成的频率精度、稳定度由什么决定？如果是由一个高精度的频率源决定的（比如铷原子钟），那么DDS频率合成过程会损失多少精度和稳定度？ |
| [答：Pascal] |
The stability of a DDS is the same as the clock which is used to drive it.
The frequency resolution is a function of the number of bits in the tuning word. ADI DDSs have either 32 or 48 bits of tuning resolution. THis means that the tuning resolution is sub-Hz.
If an atomic clock is driving the DDS, the stability of the output is as good as the atomic clock. THe frequency resolution is equal to the clock frequency divided by 2^^32 or 2^^48.
|
[2005-3-4 11:05:26] |
| [问：icy2527] |
请问专家：DDS的信号杂散是如何产生的，有什么既简便又有效的方法抑制杂散？还有关于DDS的功耗问题。谢谢！ |
| [答：Jing] |
There are a lot of factor that will result in SPUR. Generally, clock,phase transcate, phase-amplitude mapping and DAC nnliear will result in spur . You can plan your outut frequency and calcultate the spur band according to the former presentation to minimize spur. Different DDS has different power consumption( several tens mW to 3-4W) |
[2005-3-4 11:06:18] |
| [问：hansongbeijing] |
1,此频率合成器是否可以实现以及如何实现相位调节?
2,相位调节的精度如何?
3,输出宽带正弦信号的带宽范围是多少?
4,是否可用此芯片作为,实现提高A/D的SFDR指标技术中,所增加的dither(抖动)源信号.若可以如何实现?
|
| [答：Yiming] |
I don"t know which part are you asking. Please give me your part number information. Thanks |
[2005-3-4 11:07:54] |
| [问：jx_ustc] |
AD9851用在短波调相性能如何？ |
| [答：Forest] |
AD9851在短波调相性能很好，完全适合。你可以参考ADI 网页上的应用参考文章AN-587。 |
[2005-3-4 11:08:13] |
| [问：hamber007] |
PLL和DDS的组合有什么好处?主要应用在什么地方? |
| [答：Pascal] |
The benefit of using PLL with DDS is that the DDS output frequency can be translated to a higher frequency band, and a wider bandwidth. This is often used in wireless and radar applications. It is also used in clocking applications, to generate GHz clock signals. |
[2005-3-4 11:09:23] |
| [问：yufeiqun2004] |
你好，DDS的DAC导致的杂散输出频谱目前有没有精确的数学模型进行预测？
|
| [答：Fountain] |
DAC non-linearity and non-ideal switching characteristics are responsible for the highest magnitude spurs, and surely most of these spurs can be predicted or calculated, for detailed information, you can find them in the application note: DDS design, you can find it in our website, or you can just send the request to china.support@analog.com, we"ll send to you immediately |
[2005-3-4 11:09:34] |
| [问：zhaoxin79] |
怎样减小DDS的频谱杂散?
现有什么算法可以有效的缩小DDS系统中ROM表的逻辑资源？
怎样提高DDS的频率？
在FPGA中设计DDS需要注意哪些问题？ |
| [答：Richard] |
减少杂散的关键是要让这些杂散频率落到你需要的带宽之外，预测这些杂散的关键，是要找出这些杂散在没有折叠回第一Nyquist区之前与基频之间的谐波关系。无论控制字或参考时钟频率如何变化，这些杂散和基频之间的谐波关系都会保持固定 |
[2005-3-4 11:10:13] |
| [问：dboyman] |
目前，我们在做DVB—S发射机/高频测试仪的项目，预在系统中产生900M-2100M的本振，实现自动扫频功能。但是由于现在产品中的VCO的范围无法满足要求，不知该采用何种策略解决这一问题？谢谢！ |
| [答：David] |
We don"t know of any one VCO that can tune over that wide range. The only way is to configure multiple VCOs that can be switch in and out. |
[2005-3-4 11:10:18] |
| [问：阿里巴巴] |
具你们的宣传资料介绍， DDS在频率分辨率和可编程方面提供了最佳的性能。但是DDS的输出频谱包括了基频，谐波频率，镜像频率和杂散频率。我想了解一下用DDS做PLL的时钟，用于150MHZ的SSB通信设备的一本振（步进50HZ），低耗电量、低价格的AD9834之类芯片是否能够满足相位噪声要求？
|
| [答：Jing] |
AD9834 is a 50M DDS . You can use it as the clock of a PLL . It can be used as a LO in SSB . By the way, It also depend on your requirement of the phase noise . |
[2005-3-4 11:10:59] |
| [问：lm_buaa] |
镜频抑制比是怎么定义的，多谢。 |
| [答：Richard] |
镜频抑制比是当存在镜像频率的无用信号时，接受机接收标准有用信号而不超出规定恶化量的能力的量度 |
[2005-3-4 11:13:19] |
| [问：wqxh2002] |
如何规划一个输出频率为430~470MHz的跳频频合，其频率转换时间小于10uS. |
| [答：Pascal] |
In order to achieve the settling time of 10us, it is not possible to use a PLL. It is possible to sweep or jump frequency with a DDS with zero settling time. The problem is which DDS to use to cover the freq to 470MHz. The AD9858 could be clocked slightly over 1GHz, in order to give a maximum 1st Nyquist zone output up to 470MHz. Perhaps another frequency plan could utilize the second Nyquist zone to get the 430 to 470MHz with a lower DDS clock. This could be done, but would need some thought to get the right frequency plan. |
[2005-3-4 11:14:10] |
| [问：renmingcan] |
DDS在频率分辨率、跳频速度和可编程方面提供了最佳的性能,要想更全面的发挥性能，是不是需要和PLL等技术结合？ |
| [答：Fountain] |
You are right.
DDS is a good choice in many applications, but if you want to get the optimal result, you need the combination of high performance external reference clock, good low pass filter and the PCB layout, also the PLL for high frequency applications |
[2005-3-4 11:14:54] |
| [问：data_man] |
INVERSE SINC 功能是否是加窗？在什末情况下使用？使用后会得到什末样的结果？ |
| [答：Yiming] |
1. No, INVERSE SINC can compensate the amplitude drop due to the SINC effect in the higher frequency band.
2 & 3. In the higher frequency band, especially using the image frequency appliations, this function can get high SFDR. Because the signal"s amplitude is larger compared to disable INVERSE SINC function. |
[2005-3-4 11:14:59] |
| [问：liuyaxin] |
选择DAC转换芯片要看的关键技术指标是什么
|
| [答：Richard] |
DAC主要的指标就是DAC的转换时间（速度）， 精度，输入信号范围，和供电电压等。 基本上选择DAC就是看这些技术指标 |
[2005-3-4 11:15:28] |
| [问：mountchen] |
如果要想产生线性调频信号，则DDS芯片该如何来选择？ |
| [答：Jing] |
I don"t know if you are interested in frequency sweeping . If it is,you can use AD9858 ,AD9952,AD9954 |
[2005-3-4 11:17:03] |
| [问：csrwgs] |
在高频采样的过程中
您是采用哪种技术保证信号的完整性的？
谢谢 |
| [答：Pascal] |
High freqeuncy sampling requires very low jitter in order to achieve maximum signal integrity. Right now ADI is introducing a series of clock parts (AD9510, AD9511, AD9512, AD9540) which achieve less than 1ps jitter at up to 800MHz (1500MHz AD9540). The low jitter allows data converters to achieve better SNR at higher analog in frequencies. |
[2005-3-4 11:17:16] |
| [问：318007eei] |
一个10MHz的方波
信号，如果要得到10MHz的sin与cos信号同时输出，如何实现 |
| [答：Richard] |
AD9854就可以实现，请参考数据手册 |
[2005-3-4 11:18:01] |
| [问：zhangjialiang] |
当前DDS技术能做到多大的频率和分辨率呢，输出功率多大，驱动如何，如果10兆的频率，能做到多大的带宽和分辨率 |
| [答：David] |
The highest sampling DDS is 1GHz, the AD9858.
The AD9858 has 32-bit frequency tuning resolution and a 10-bit DAC.
The AD995x runs at 400Mhz, it has 32-bit frequency resolution and a 14-bit DAC.
Typically, the fullscale DAC current is set to 5mA to 20mA (pk to pk). |
[2005-3-4 11:18:19] |
| [问：skycity1221] |
是否有8bit内部DAC的DDS
|
| [答：Jing] |
No. Our internal DAC is 10bit,12 bit and 14bit |
[2005-3-4 11:19:19] |
| [问：hamber007] |
如何适当选择DDS?主要考虑的因素是频率还是稳定度? |
| [答：Fountain] |
There"re many specifications you need to consider, e.g. frequency resolution, frequency, also the output supurs, it depends your application |
[2005-3-4 11:20:39] |
| [问：318007eei] |
PLL放大倍数对时钟稳定度的影响如何？ |
| [答：Pascal] |
The multiplication factor of the PLL increases the phase noise of the signal. The phase noise increases by the factor of 20*log(F2/F1). This is a result of physics. It is possible to post filter the output of the PLL with a Band Pass filter if the frequency is fixed. This can improve the wideband phase noise considerably. However, if the frequency must be tunable, the BP filter is not an option. |
[2005-3-4 11:21:14] |
| [问：skycity1221] |
dds主要应用于哪些领域? 相比之下与软件频率合成有哪些优势?
|
| [答：Richard] |
DDS广泛地应用于通信，军事，仪器仪表中，用于产生时钟，可变频率信号，和数字锁相环。 与软件频率合成相比，它的集成度，相噪，以及稳定度都更好 |
[2005-3-4 11:22:35] |
| [问：bj-mw] |
请问：我们准备用AD9858芯片制作200MHz－400MHz的扫频信号源，其杂散频谱电平能否低于－50dB？或者，您有好的建议请告诉一下。谢谢。 |
| [答：David] |
I don"t think the SFDR over that range is better than -50dbc. |
[2005-3-4 11:22:46] |
| [问：shaoboxu] |
我最近要购买AD9858希望知道该芯片的应用电路，以及应用的一些关键主意点我信箱shaobo_xu@163.com |
| [答：Fountain] |
you can download the evaluation board documents and related application notes from our website: www.analog.com, or you can send your request to china.support@analog.com, we"ll respond ASAP |
[2005-3-4 11:23:28] |
| [问：rdli] |
请介绍合成器输出频谱纯度和相位抖动的估算 |
| [答：Forest] |
我们的DDS产品内部都有一个多位的频率寄存器，例如即使是一个具有32 位累加器的1 GHz的DDS可以具备0.23赫兹的频率分辨率，1GHz/2^32。而且内部也都有一个相位寄存器，同样可以进行相同的计算，来得到频率和相位的估算。 |
[2005-3-4 11:23:31] |
| [问：hansongbj] |
可以用DDS产生混频器（MIXER）的参考信号源吗？，目的是对3.5MHz中心频率窄带信号进行正交解调。这种应用是否要求频谱纯度很高？请推荐一款芯片。 |
| [答：Jing] |
Yes , you can use DDS as the REF clock of MIXER. Of cause the pure the better. So you should planning you output frequency of DDS .YOu can use AD9953/4. |
[2005-3-4 11:23:40] |
| [问：yqy329] |
影响DDS频率精确度的因素初了振荡本身的频率精度外,还有那些因素? |
| [答：Wenshuai] |
We discussed the follwoign sources:
1. Ref Clock Spurs
Phase Truncation Spurs
Angle-to-Amplitude Mapping Spurs
DAC Quantization Spurs
Digital Clock Spurs |
[2005-3-4 11:24:12] |
| [问：vvvzhzhh] |
对于信号发生器的开发来说，DDS芯片很重要，内置PLL能不能满足高精度要求？
还有就是选择内置PLL芯片，有什么比较划算的算法？ |
| [答：Pascal] |
The on-chip PLL of the AD9956 (for example) will have the same frequency resolution of the DDS, but only decreased by the frequency multiplication factor. For example, if the PLL is 2X, then the frequency resolution of the DDS reduced by one-half.
I don"t understand the rest of the question. |
[2005-3-4 11:24:46] |
| [问：xlstyle] |
你们是如何保证频率稳定度的？ |
| [答：Pascal] |
The stability of the output of a DDS is directly proportional to the frequency stability of the clock source which is driving it. The output of a DDS is always an exact fraction of the clock, and tracks the clock frequency in proportion to the tuning word. |
[2005-3-4 11:26:34] |
| [问：shaoboxu] |
请问AD9858的输出功率是多少？
其典型应用原理图？ |
| [答：Jing] |
The power consuption is less than 1.9W .For schematic files, I can patch it here .You can contact 800 810 1742 to get the circuit. |
[2005-3-4 11:26:40] |
| [问：data_man] |
请问：可不可以在DDS的存储器中写入数据，使其输出任意波形？ |
| [答：Richard] |
DDS的输出信号频率通常来说，只能低于参考频率的40％。但在ADI的某些DDS器件中，参考时钟经过倍频，输出可以超过输入信号频率。但是输出信号只能为 SIN or COS 波形 |
[2005-3-4 11:26:44] |
| [问：shaoboxu] |
时钟参考源用锁相环倍频后是否还要把幅度放大到5V?谢谢！ |
| [答：Fountain] |
The reference clock logic of our DDS commonly are CMOS and TTL, for specified part, you can refer to related datasheet |
[2005-3-4 11:27:18] |
| [问：playyz] |
AD9857AST问题：
1。引脚PS0和PS1含义不清楚，怎样使用？2。引脚SYSCIO含义不清楚，怎样使用？ |
| [答：Yiming] |
1. The are used to select the pre-configured our profile configurations. please see the matrix in the datasheet.
2. If you want to abort the current serial port communication without affect the addressable registers contents, you can give a high on this pin. when it goes low, another searial port communcation can begin. |
[2005-3-4 11:27:40] |
| [问：guahuahua] |
DDS的频率是指它的输出时钟的速度吗？一般DDS可改变多少个点 |
| [答：Forest] |
DDS的频率一般是指输入时钟的频率，在数据手册上你可以看到REF Clock和Output Clock这两个参数。一般DDS内部都有一个频率寄存器，寄存器的位数决定可以输出的点，2^N个。 |
[2005-3-4 11:27:57] |
| [问：shiwenyuan] |
请问主持人:按照P24的讲稿,如果采用较高的参考频率,AD995X是不是目前性能最好的? |
| [答：Pascal] |
The AD995X series of DDS has a clock frequency of 400MHz. These are the recommended DDS for this clock frequency range at this time. |
[2005-3-4 11:28:04] |
| [问：yqy329] |
目前1000MHz的DDS的精度能达到多少? |
| [答：Jing] |
You can get 0.23Hz frequency resolution with our 1G AD9858. |
[2005-3-4 11:28:27] |
| [问：lirbert] |
ADI 有没有DDS输出滤波器的设计参考 |
| [答：Jing] |
Yes . you can contact with 800 810 1742 to get some crresponding artical for this application. |
[2005-3-4 11:29:29] |
| [问：uestcpony] |
请问：
1.如何彻底消除频率合成中的信号串扰问题？
2.在DDS合成方法中，如何使杂散抑制最好？
谢谢！ |
| [答：David] |
Things to try to reduce coupling:
1) Seperate digital and analog supplies and provide good bypass of power supply pins.
2) Use transformer or differential coupling for the
DAC output to provide common-rejection.
|
[2005-3-4 11:29:41] |
| [问：wang.xiang] |
请介绍相位累加器对DDS性能的影响有多大? |
| [答：Fountain] |
The tuning word mainly affects the frequency resolution |
[2005-3-4 11:30:36] |
| [问：agen] |
In our 9854 design, the output signal only perform well when its freq is near 20% of freq. of REFCLOCK,(PLL is not used) what is the matter? |
| [答：Pascal] |
What problem are you seeing above 20%?
Is it possible that your reconstruction filter is not functioning correctly?
Is the performance bad only at certain frequencies and good at others? Could it be folded back harmonics?
We would need to know more to answer this question completely. |
[2005-3-4 11:30:59] |
| [问：realfan19820701] |
请问AD公司的DDS是基于FBGA的解决方案吗？这样就可以根据需要方便地实现各种比较复杂的调频、调相和调幅功能 |
| [答：Forest] |
DDS不是基于FPGA的解决方案，它并不能进行编程，只能进行内部寄存器的修改。AD9954只具有有限的编程能力。 |
[2005-3-4 11:31:40] |
| [问：hzzhangxin] |
DDS相对带宽宽,频率转换时间短,具体的指标是什么？ |
| [答：Yiming] |
DDS can output 0~0.4*fclock frequency. This is output frequency range spec.
The second spec means its agile ability in frequency hopping.
|
[2005-3-4 11:33:19] |
| [问：liboc] |
ADI公司的有些DDS芯片内部带有反sinc滤波器（在DAC前面），但可以选择使用或旁路。能否对是否使用反sinc滤波器给一些建议？ |
| [答：Jing] |
You can refer to AD9857,AD9856. AD9857 can bypass SINC filter . Generaly, the amplitude of the output of the fundermental frequency will decrease with the increase of the output frequency .If you use inverse SINC filter , you can overcome this phenomenon. |
[2005-3-4 11:34:38] |
| [问：data_man] |
请问：AD9857中的profile是什麽含义？ |
| [答：Wenshuai] |
The settings for one frequency case. If you wanted to know the details, feel free to contact us via china.support@analog.com, or the toll-free number 800 810 1742. |
[2005-3-4 11:35:16] |
| [问：skycity1221] |
对于8bit的数据流使用10bit的DDS，剩余的数字脚在pcb中如何处理？输出信号是怎样的？ |
| [答：Richard] |
10bit是指芯片里的DAC精度，但与DSP/MCU接口通常是8位 所以不影响你使用 |
[2005-3-4 11:35:28] |
| [问：wang.xiang] |
DDS的基准时钟对DDS的杂散信号影响有多大?是时钟的毛刺还是谐波? |
| [答：Forest] |
DDS的基准时钟的性能会很大的影响输出信号的性能。参考时钟的杂散频率会以相同的固定频率偏移传递到DDS的输出。参考时钟的噪声会以同样的方式传递到DDS的输出。DDS输出的参考时钟杂散或噪声的幅度会随着控制字的减小而减小，可以用下式表达：dBc = - 20 log(参考时钟频率/DDS输出频率)， 如果使用了内置参考时钟倍频器，参考时钟的所有噪声和杂散都会在PLL环路带宽内按照下式放大：dBc = 20 log(参考时钟的倍频数4倍～20倍)。时钟的毛刺和谐波都会影响。 |
[2005-3-4 11:36:03] |
| [问：shaoboxu] |
AD9858的参考时钟1G是用外部PLL好些还是内部PLL好些？ |
| [答：Jing] |
If you want to get better performance, you should use external high performance PLL and VCO. |
[2005-3-4 11:36:15] |
| [问：coimhuang] |
对于要产生1575MHz、575MHz、325MHz的正弦频率，可选用你们什么型号产品 |
| [答：Yiming] |
Your can select our PLL products, such as ADF4113 (Integer product), ADF4153 (Fractional product). |
[2005-3-4 11:36:28] |
| [问：yqy329] |
能否在DDS输出频率上直接进行调频?如果不行,采用什么办法?有电路图吗? |
| [答：Pascal] |
It is not possible to FM modulate the output of the DDS after the DDS, that is, after the DDS.
It is possible to FM modulate the signal in the DDS by varying the DDS tuning word, or setting different frequencies in the frequency profile of some DDSs. The bandwidth of the modulation is dependent upon whether you want to do shaped bi-level or multi-level FM, or emulate analog FM. The exact needs of the modulation would need to be matched to the DDS model and its specific capabilities. |
[2005-3-4 11:37:09] |
| [问：myw] |
我利用AD9851产生HF频段的信号，是否需要在器件结构上采用屏蔽措施？ |
| [答：Richard] |
采用屏蔽可以提高这一部分的抗干扰能力，是否有必要采用要综合你整个产品的应用和需求 |
[2005-3-4 11:37:50] |
| [问：hube0728] |
dds集成电路中的数字地属于
高频地还是低频地 |
| [答：Wenshuai] |
Please connect it to the AGND. For further technical support, call 800 810 1742 or china.support@analog.com. |
[2005-3-4 11:38:11] |
| [问：goodman302] |
如果要生成一路正弦,三路方波那么需要四片DDS芯片吗? |
| [答：Fountain] |
It depends, AD9834 can output square waveform directly, for high frequency application, you can choose DDS parts with on board comparator, and AD9852/AD9854 can output I-Q waveforms |
[2005-3-4 11:38:25] |
| [问：SONGCAIJUN] |
我现在板子上的AD9854AST的SYSCLK要是在120MHZ左右以上的时候AD9854AST就坚持不了一会就没有输出了,有什么可能的原因? |
| [答：Yiming] |
When it works at > 100MHz, it will be very hot. I recommend you to add a fan to cool this part. |
[2005-3-4 11:39:12] |
| [问：chenhgl] |
内部PLL产生的杂散会被以20LOGX全部放大,那么采用外部PLL的方式,是如何计算的呢?有公式吗?
|
| [答：Dan] |
When external PLL output is used to clock the DDS, the PLL noise is treated as reference clock nosie and please refer to the presentation for reference clock noise calculation. |
[2005-3-4 11:39:26] |
| [问：yaotingyan] |
DDS输出低通滤波器采用椭圆滤波器是出于什么考虑？如果换用其他类型的低通有什么不同？ |
| [答：Pascal] |
An elliptical filter is used because it has very low inband ripple, and a steep transition to the stop band. However, it does not have low ripple in the stop band. If low ripple in the pass band is not needed, then other filters, such as Chebychev, may work as well or better than the elliptical. |
[2005-3-4 11:39:28] |
| [问：mountchen] |
请问DDS芯片如果想应用在高动态扩频信号源的设计中，哪种型号的比较合适？ |
| [答：David] |
The AD995x series DDSs probably have the best SFDR.
If phase noise is important, you should drive the
REF CLk on the AD995x family with a stable source with high slew rate. |
[2005-3-4 11:39:37] |
| [问：kedadizhi] |
除了采用多个DDS合成多频率波形外，有没有产生多频率合成波形的DDS芯片。我认为DDS有产生多频率合成波形的能力 |
| [答：Jing] |
I don"t know if your question focus on MIXER? You can refer to our AD9858,it has a mixer in it that can combine different frequency. |
[2005-3-4 11:40:12] |
| [问：wangxin] |
DDS是否可以通过输出缓冲，直接作为输出？ |
| [答：Wenshuai] |
Yes. But, you should consider whether its amplitude can meet your requirrement. Maybe an amplifier will be used follows DDS. |
[2005-3-4 11:40:35] |
| [问：wjbwywy] |
请问你们的工业仪表仪器类的DDS系列都有那些？有什么特点？ |
| [答：Forest] |
我们所有DDS产品都适合于工业仪表，我们的产品系列比较全，输出频率的分辨率高，相位可以控制调整，可靠性高，都属于工业级的产品。 |
[2005-3-4 11:42:15] |
| [问：austinfu] |
Hi,I"m student.Now,I want to use DDS device in Jump－Frequency Communication System.Can you recommend a device of your company? And is there somthing I should pay more attention to especially? |
| [答：Pascal] |
Yes, DDS can be used in a frequency hopping system. What is the frequency range that is needed? What is the hopping rate? If the output of the DDS needs to be increased, it could be a problem to use direct PLL upconversion, because the frequency hop settling time becomes a function of the PLL loop, and the advantage of DDS zero settling time is lost. It is preferable in that case to use upconversion (mixing) to achieve higher frequencies. |
[2005-3-4 11:42:24] |
| [问：goodman302] |
How to predict phase-to-amplitude spurs in their freqency location? |
| [答：Richard] |
You can find it in the presentation showed today. Moreover, you can get help in ADI interactive tool online http://www.analog.com/Analog_Root/static/techSupport/designTools/interactiveTools/ |
[2005-3-4 11:42:37] |
| [问：playyz] |
现在哪些DDS是要LICENSE的,比如AD9854,AD9857,AD9954会有吗? |
| [答：Jing] |
Now,our DDS don"t need license. |
[2005-3-4 11:43:24] |
| [问：leo1981cn] |
Is it unfeasible to realize 18-bit DDS using FPGA and 18-bit DAC because of its long output settling time? |
| [答：David] |
I would think it"s feasible, but you would not get
18-bit ENOBs (ac performance) |
[2005-3-4 11:43:24] |
| [问：kedadizhi] |
我想问，是否有一次能发送多频率合成波形的DDS芯片。
|
| [答：Jing] |
You can use AD9858. It has a mixer in it. |
[2005-3-4 11:43:48] |
| [问：lzs1997] |
ADI公司的DDS与其他公司比较，有什么优越性？ |
| [答：Pascal] |
Which competitors? Other DDSs?
ADI DDS products are leaders in high frequency, high resolution, high functionality DDSs. |
[2005-3-4 11:44:04] |
| [问：jerryyeung001] |
DDS和模拟PLL相比有何特点? |
| [答：Jing] |
DDS
Extremely high frequency resolution
Agile – no settling time or overshoot for frequency shifts
Can be phase and amplitude modulated
Multiple DDSs can be synchronized
Inherently digitally controlled
Requires DDS clock more than 2X desired output frequency
Requires external reconstruction filter
Higher frequency operation requires more power
Output frequency limited to less than half of DDS clock frequency
PLL
VCO is a critical component
Integer-N PLL design limits frequency resolution
Loop settling characteristics affect settling time and overshoot during frequency shifts
Loop multiplication factor increases phase noise of RF
Can achieve GHz frequencies
Fractional-N design achieves good frequency resolution
Can be very low power
Does not require reconstruction filter
Reference frequency lower than output frequencies
|
[2005-3-4 11:45:12] |
| [问：htc703] |
In DDS, I think filter is very important. How to design DDS"s filter? Would you like to give some advice? Thanks! |
| [答：Forest] |
we recommend that you select 5 or 6 order filters, you can find the really schematic in the evaluation board. |
[2005-3-4 11:46:43] |
| [问：jerryyeung001] |
如何设计DDS的输出滤波器?能否用AD9850为例来说明? |
| [答：Wenshuai] |
Normally, the easiest way is to refer to our EVB. For example, you can find the AD9850 filter from its EVB design. For further technical support, contact us via 800 810 1742 or china.support@analog.com. |
[2005-3-4 11:47:08] |
| [问：jerryyeung001] |
目前DDS的SPUR能达到多高的水平? |
| [答：Pascal] |
THe AD995X family has a narrow band SFDR (spurious free dynamic range) of 85dBc. The wideband SFDR (zero to Nyquist)is typically no worse than 50dBc. |
[2005-3-4 11:47:09] |
| [问：zhaoxin79] |
能具体说一下，为提高dds的性能，在pcb布线方面要注意哪些？
|
| [答：David] |
Seperate digital and analog supplies.
Use differential coupling for the DAC output.
Use good bypassing for the power supply pins. |
[2005-3-4 11:48:15] |
| [问：vvvzhzhh] |
想要产生噪声信号，（我指的是有用的噪声，因为信号源的话要能提供所有波形），还有如何产生随机波形，选择什么型号的DDS电路芯片？ |
| [答：Richard] |
我认为你指的随机波形包含二部分，其一是频率可调，其二是波形可变。频率可调可以通过DDS来实现，当然输出的最大频率也是有限制的。波形可变只能通过增加额外的电路来实现，因为DDS的输出都是Sin信号。 选择什么样的DDS要根据你所需要的频率和相噪来决定 |
[2005-3-4 11:48:56] |
| [问：qingfengjiang] |
DDS的相位噪音受那些因素影响?基准时钟的抖动是否是主要原因? |
| [答：Jing] |
The clock noise, the reconstruction filter and the will result in phase noise. Yes, the reference clock is a major factor. |
[2005-3-4 11:48:58] |
| [问：goodman302] |
ADI公司的DDS芯片产生正弦波的频率有没有下限,在什么频段最理想? |
| [答：Forest] |
我们输出的下限就是分辨率的最小值，你可以根据频率寄存器的位数进行计算。我们建议你的输出频率在你输入频率的40%以下。 |
[2005-3-4 11:50:58] |
| [问：wangyan_lucky] |
如何消除DAC的非线性和量化噪音对DDS性能的影响? |
| [答：Fountain] |
The noise generated from the DAC can not be eliminated, but you can use some tricks to reduce its effect, e.g. use low pass filter to block the supurs, for detailed information, we have a good DDS tutorial in our website,if you have other questions, please send to china.support@analog.com, we"ll respond ASAP |
[2005-3-4 11:51:10] |
| [问：BG4REO] |
在制作AD9850的PCB时应当注意些什么?谢谢!
|
| [答：Yiming] |
1). Good power decoupling.
2). Use a 4-layer PCB, Seperate power layer and ground layer.
For more detailed information please see Page 13. REV.E of AD9850"s Datasheet. |
[2005-3-4 11:51:19] |
| [问：cocow0222] |
AD9858使用CPLD/FPGA控制，但是DDS输出与CPLD的时钟信号不同步，如何解决？ |
| [答：Wenshuai] |
You can use the same RESET to reset both your CPLD/FPGA and AD9858. You can refer to our AN587. If you need further technical support, feel free to contact us via china.support@analog.com or 800 810 1742. |
[2005-3-4 11:51:57] |
| [问：joe_cheng] |
What should I take care when the output frequency is much larger than the reference frequency. ex 1800 times?? |
| [答：Richard] |
Generally DDS can not do it ( 1800 times output frequency than reference clock ), and you need multi PLL to implement it |
[2005-3-4 11:52:37] |
| [问：xmm] |
直接数字频率合成能否用于无线话筒设计？功耗？价位？方便性？
还想了解更多，3月4号会来学习！ |
| [答：David] |
Right now, the power comsumption for DDS is probably too high for wireless microphone application.
The AD995x family is runs about 180mW at 400MSPS.
It less as the sample rate is decreased. |
[2005-3-4 11:52:48] |
| [问：vvvzhzhh] |
请问对于信号发生器的开发，采用DDS电路，输出是否需要精密滤波电路？如果需要，产生调频信号怎么办？ |
| [答：Yiming] |
The 3dB bandwidth of the low band pass filter should be limited to the maximum output frequency. |
[2005-3-4 11:54:07] |
| [问：qingfengjiang] |
请介绍ADI的DDS参考设计工具的性能和价格. |
| [答：Jing] |
You can log into http://www.analog.com/en/prod
/0%2C2877%2CAD9954%2C00.html to check the price and our DDS reference design |
[2005-3-4 11:54:08] |
| [问：uestcpony] |
我们打算采用AD9956芯片来设计一个2GHz左右的跳频源，请问设计的最佳带宽可以达到多少？其最佳的相噪和杂散指标如何呢？谢谢！ |
| [答：Pascal] |
The bandwidth at the 2GHz band will be determined by the VCO which is used. The system requirements for phase noise may dictate that a narrower range VCO be used. The tuning voltage and the tuning range of the VCO are often tied to its noise performance.
The phase noise will be determined by the VCO characteristics (wideband) and the loop filter (narrow band). The DDS adds very low phase noise to its clock source, which should be low phase noise, because its phase noise shows up on the DDS output. However, the PLL can modify the phase noise characteristics considerably.
In other words, the answer to your question can be complex. There are several considerations. |
[2005-3-4 11:54:56] |
| [问：coww1980] |
我用的是AD9854,串行配置，外部UPCLK，是不是一定要先对工作方式进行配置，再开时钟，然后在写控制字啊。我是直接开时钟然后进行配置的，怎么点频方式可以，其他都不行啊
|
| [答：Richard] |
如果你是用Update,确实是要先配置，再开时钟，写控制字。如果是内部UPCLK，就没这个问题 |
[2005-3-4 11:55:29] |
| [问：goodman302] |
DDS的最高工作频率以及噪声性能能达到锁相频率合成器相当的水平吗? |
| [答：David] |
It depends on the application.
|
[2005-3-4 11:56:17] |
| [问：liying54321] |
请提供可选用DDS的频率和稳定度的参数。 |
| [答：Yiming] |
1. frequency spec: the maximum output frequency (0.4* fsysclock)
2. The stability spec depends on the reference. |
[2005-3-4 11:56:30] |
| [问：yunyt] |
我不明白DDS为什么能产生正弦波输出信号,能解释一下吗? 正弦波的性能如频率和噪音和那些因素有关? |
| [答：Fountain] |
For the operation theory, we have a DDS tutorial in our website, you can download from www.analog.com/dds, the frequency and frequency resolution have relation to tuning word. The output noise mainly generated by DAC, reference clock and PHASE TRUNCATION |
[2005-3-4 11:56:39] |
| [问：shiwenyuan] |
请问有SPI接口的DDS芯片吗?它的控制位刷新率多少? |
| [答：Richard] |
有很多DDS, 如AD9854都支持SPI接口，具体的控制位刷新率要参考数据手册 |
[2005-3-4 11:59:14] |
| [问：yunyt] |
多个DDS可以同步工作吗?DDS输出的相移有多大?作这样使用时要注意什问题? |
| [答：Yiming] |
Yes, please launch our website: http://www.analog.com, there is an application notes : AN-605 which describes this issue. |
[2005-3-4 11:59:47] |
| [问：jerryyeung001] |
DDS+PLL的频率范围和噪音比单独DDS有何优点? |
| [答：David] |
Using a PLL in combination with DDS can provide
much higher frequency range. In addition, the PLL
can act as a tracking filter for the DDS output spectrum by narrowing its loop bandwidth. |
[2005-3-4 12:00:58] |
| [主持人：ChinaECNet] |
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[2005-3-4 12:01:18] |
| [问：skycity1221] |
对于500Mhz,8比特3.3v数据流来说,采用那款DDS比较合适？
|
| [答：Pascal] |
I assume that you mean that you have 8-bit parallel data at 500MHz that you want to use to modulate an RF signal. This data rate is too high for our quadrature digital modulator DDS chips (such as the AD9857 - up to 50MSPS @ 14-bits I/Q).
I would need to understand the application better to make a recommendation. |
[2005-3-4 12:01:51] |
| [问：lixb] |
DDS频率合成器是否有相位噪声？频率稳定性是否受相位噪声的影响？ |
| [答：Yiming] |
1. Yes.
2. DDS"s stability can not be effected by phase noise. |
[2005-3-4 12:03:54] |
| [问：leon_zhou] |
请介绍相位累加器对DDS的影响.谢谢! |
| [答：Fountain] |
The phase register mainly add the tuning word value to generate the specific frequency |
[2005-3-4 12:04:44] |
| [问：felix2yk] |
请问对于贵公司的AD9857进行IQ调制时，是否输入I、Q的数据率应当满足与参考时钟的某一个公式，还是只要工作在小于，参考时钟、工作模式（内插的数目、反sinc滤波等）所允许的最大I、Q速率之下就可以。我的理解是：工作模式选定，只要输入数据率小于，芯片进行内插滤波、调制所引起的最大时延就可以。谢谢 |
| [答：Yiming] |
For the modulation mode, the input data rate depends on the system clock, interpolation rate. |
[2005-3-4 13:09:54] |
| [问：data_man] |
当用AD9857AST输出任意波形(例如SINC函数波形）时，是否使用插补DAC方式？此时内部的CIC和INVERSE SINC FUNCTION是否使用？ |
| [答：Yiming] |
You can use this mode to generate arbitrary waveform. The inner CIC and INVERSE function can be used. The INVERSE function can compensate the output amplitude"s roll-off due to the sampling pulse"s SINC effect. |
[2005-3-4 13:18:40] |
| 非在线问答： |
| [问：] |
AD9858同其他厂家的同类芯片相比有什么优势？ |
| [答：] |
AD9858内部10位高精度DAC 可以达到1GSPS，输出可以达到400MHz, 并且内部集成电荷泵和鉴相器。同时内部还有混频器，可以完成更多的功能。 |
| [问：] |
AD995x的功耗指标？ |
| [答：] |
在1.8V工作电压下，功耗大约在160mW左右 |
| [问：] |
ADI的DDS产品的SFDR能达到多高的水平? |
| [答：] |
在宽带SFDR可以达到约64dB, 在窄带SFDR可以达到约85dB |
| [问：] |
ADI的DDS的输出阻抗都是50欧的吗 |
| [答：] |
ADI的DDS的输出都是电流输出 |
| [问：] |
ADI的DDS器件和MC145158相比有何优势,在性能和价格上? |
| [答：] |
For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
ADI那些DDS产品具有FSK编码器功能? |
| [答：] |
没有. But you can use DDS to implement it. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
ADI有没有关于DDS用在FM收音机的解决方案?能否提供电路原理图? |
| [答：] |
没有. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
ADI有没有关于DDS用在卫星广播接收器方面的解决方案? |
| [答：] |
没有，但是已经有其他客户采用DDS 产品来实现. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
ADI有没有关于DDS用在卫星广播接收器方面的解决方案? |
| [答：] |
没有，但是已经有其他客户采用DDS 产品来实现. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
adi有没有针对汽车电子控制行业上的典型应用实例 |
| [答：] |
Can you let us know the details of your system requirements? In fact, many of our parts are used in automotive applications.For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS得时钟最大能够达到多少?产生的信号带宽最大多少？ |
| [答：] |
DDS现在最大的时钟可以达到1G，但是我们推荐输出的时钟在输入时钟的40%以下. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS的电源是否采用线性电源要比开关电源要好? |
| [答：] |
Yes, It's better to use linear power supply. It will be less ripple wave. But you can also use switched power supply with good power decouple circuit. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS的功耗相对较大，芯片较热。有没有较小功耗的芯片。 |
| [答：] |
Yes,we have some low power DDS. Such as AD995X,AD9831/2/4. It also depend the clock frequency of DDS. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS的驱动能力如何？比如要将一个DDS的输出作为32路混频器的参考源，用什么方式驱动？驱动后的相位一致性如何保证？ |
| [答：] |
It depend on the output DAC capacity .All ADI DDS's DAC is current output (5mA---20mA). For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS的输出滤波器采用带通和低通型有何差别? |
| [答：] |
We use ellipse low pase filter. Because we need to filter the image of the fundamental wave. For some applications, you have to use bandpass filters. For example, you wanted to use the image signals. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
dds的输出滤波器是取低通滤波器还是应该取带通滤波器，二者的区别在哪里 |
| [答：] |
We use ellipse low pase filter. Because we need to filter the image of the fundamental wave. For some applications, you have to use bandpass filters. For example, you wanted to use the image signals. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS的输出频率和取样频率的关系比例对输出信号杂散 |
| [答：] |
The output frequency is less than 40% of the clock frequency to minimize the image component influency and increase SFDR |
| [问：] |
DDS的输出频率受那些因素的影响? |
| [答：] |
Generally, FTW and the master clock is the key factor. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS的主要应用在哪些方面？ |
| [答：] |
Mainly in three field: 1, Wave generator;2, Frequency synthesizer,3, Modulator. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS供电电压范围是多少?起输出高低电平是否随供电电压而不同? |
| [答：] |
Different DDS has different power supply range. For example, we have1.8V,2.5V3.3V,5V product. The output level will be different too. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS和模拟PLL相比有何特点? |
| [答：] |
For PLL:Can achieve GHz frequencies
Fractional-N design achieves good frequency resolution
Can be very low power
Does not require reconstruction filter
Reference frequency lower than output frequencies VCO is a critical component
Integer-N PLL design limits frequency resolution
Loop settling characteristics affect settling time and overshoot during frequency shifts
Loop multiplication factor increases phase noise of RF
For DDS: Extremely high frequency resolution
Agile – no settling time or overshoot for frequency shifts
Can be phase and amplitude modulated
Multiple DDSs can be synchronized
Inherently digitally controlled
Requires DDS clock more than 2X desired output frequency
Requires external reconstruction filter
Higher frequency operation requires more power
Output frequency limited to less than half of DDS clock frequency. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
DDS可实现的工作带宽是多少？ |
| [答：] |
请致电 800 810 1742 详谈 |
| [问：] |
DDS输出频率的谐波,杂散以及相噪如何? |
| [答：] |
每个DDS因为其内部的DAC的速度（时钟），精度不一样，以及所要求的输出频率不同， 所以它的谐波，杂散，和相噪都不一样。具体可以参考每个DDS的数据手册 |
| [问：] |
DDS输出信号频率变化是否和相移一起改变? |
| [答：] |
DDS的输出信号的频率和相位是可以通过控制芯片（DSP或MCU)单独控制的 |
| [问：] |
DDS输出信号频率变化是否和相移一起改变? |
| [答：] |
DDS的输出信号的频率和相位是可以通过控制芯片（DSP或MCU)单独控制的 |
| [问：] |
dds芯片的基准时钟是取高频率效果好还是低频率效果好 |
| [答：] |
每个DDS都有自己的内部时钟频率，是选高频率还是低频率的DDS关键是看你需要的输出信号频率，以及你能接受的谐波幅度。相比而言，同样的输出信号频率，高频率的DDS，它的二阶谐波相隔较远 |
| [问：] |
DDS中不用的引脚如何处理? |
| [答：] |
这个问题可以参考数据手册说明，具体要看哪个引脚 |
| [问：] |
dds主要应用在产品开发的哪个部分？ |
| [答：] |
DDS主要应用在通信，仪表产品，作为时钟源，数字锁相环等等 |
| [问：] |
How many is the highest frequency by DDS produced nowadays? |
| [答：] |
ADI现有的DDS内部最高时钟为1GHz, 因此它比较适合产生400MHz以下的信号, AD9956 can be 2.7MHz. |
| [问：] |
I want to produce a FM signal,can you tell me that how much BW DDS can gets? |
| [答：] |
请致电 800 810 1742 详谈 |
| [问：] |
Is DDS, with typical parameters(for example,9854's 14bit DAC)strong enough for high quality analogy modulator(analog AM, analog FM)? |
| [答：] |
请致电 800 810 1742 详谈 |
| [问：] |
Is it unfeasible to realize 18-bit DDS using FPGA and 18-bit DAC because of its long output settling time? |
| [答：] |
I would think it's feasible, but you would not get 18-bit ENOBs (ac performance). For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
Thanks ADI experts and Presider for your presentation, can I have some material about your products? Thanks |
| [答：] |
please visit www.analog.com/dds, or tell us your address through toll free hotline 8008101742 |
| [问：] |
采用dds+直接频率合成器的方案，PLL的锁定时间通常是否可以做到100微秒以下 |
| [答：] |
PLL的锁定时间一般在几百微秒以上，PLL+DDS的方案可以实现快速的跳频. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
采用DDS的好处是什么?主要应用在那些领域? |
| [答：] |
DDS主要应用在通信，仪表产品，作为时钟源，数字锁相环等等,DDS具有超宽的相对宽带，超高的捷变速率，超细的分辨率以及相位的连续性，可编程全数字化，以及可方便实现各种调制等优越性能. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
采用FPGA实现DDS,SFDR是否会更好? |
| [答：] |
由于时钟等方面的原因，由FPGA实现的DDS往往会有更糟的SFDR. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
采用对参考时钟倍频得方法对倍频以后的频率稳定度与精度有什么影响？有具体的公式麽？ |
| [答：] |
with on chip pll to produce higher reference clock, will lead to higher phase noise, for detailed information, please refer to the presentation and download a article named 'DDS design'from our website www.analog.com/dds. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
从那里可下载有关DDS的设计资料? |
| [答：] |
please visit www.analog.com/dds. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
单片DDS的概念是什么?是否不需要外接元件?形成完整的频率发生器还需要什元件? |
| [答：] |
It means an IC integrates phase accumulator, phase to accumulator converter and DAC; to fulfill a system, you still need external reference clock, low pass filter, etc. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
当用AD9857AST输出任意波形(例如SINC函数波形）时，是否使用插补DAC方式？此时内部的CIC和INVERSE SINC FUNCTION是否使用？ |
| [答：] |
You can use this mode to generate arbitrary waveform. The inner CIC and INVERSE function can be used. The INVERSE function can compensate the output amplitude's roll-off due to the sampling pulse's SINC effect. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
发射800M -3G，接收介质产生的拉曼频率。如何产生稳定窄带可选频率？
能否长期稳定工作在125度条件下？ |
| [答：] |
could you please describe your questions more clear, you can write to china.support@analog.com or call toll free hotline 800 810 1742 for technical help |
| [问：] |
该器件是什么封装形式？几次封装？ |
| [答：] |
Which part do you mean? As to the package information, you can find it in our website. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
改变单个DDS输出信号的相移应如何操作? |
| [答：] |
It can be achieved by writing to the phase registers. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
和IBM,NS的DDS相比,ADI的SFDR性能有何优势? |
| [答：] |
Dropped. |
| [问：] |
和普通单片机相比的优势在哪里？ |
| [答：] |
Dropped. |
| [问：] |
基于DDS的RF频率合成器,频率锁定时间是多少？能否实现跳频? |
| [答：] |
Our highest speed DDS available is AD9858.It's output frequency is 400MHz. If you use only DDS to implement frequency hopping, the lock time can be in nano seconds order. If you use DDS+PLL solution to get higher frequency,different methods can get different performance in terms of lock time. For more details, you can find them from our last DDS seminar which can be found in our website. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
角度与幅度分辨率是多少 |
| [答：] |
It is determined by the resolution of the frequency tunning word and output amplitude configure register. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
模拟频率合成与dds在模拟调频应用上（语音、图像）各自优势？ |
| [答：] |
DDS的频率分辨率更高，跳频速度更快。For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
目前DDS的SPUR能达到多高的水平？ |
| [答：] |
宽带SFDR可以达到64dB多, 窄带SFDR可以达到85dB多. You can refere to the datasheet of AD9954. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
目前DDS的取样频率最高能达到多少? |
| [答：] |
DDS现在最大的时钟可以达到1G，但是我们推荐输出的频率在输入时钟的40%以下. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
目前幅度分辨率最高的DDS能达到多少？有人使用FPGA+DAC实现简单DDS功能，这个方法是否可行？ |
| [答：] |
The amlitude register of AD9852/4 is 12 bits. AD995x has 14 bits amplitude resolution. FPGA+DAC can realize DDS functions. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
目前最新的DDS芯片是那一款。 |
| [答：] |
Our lasted released part is AD9954 series, AD9956. And many new parts are to be released. For details, visit our website www.analog.com or contact 800 810 1742, please. |
| [问：] |
那镜频抑制比如何计算哪，我们如何评定性能。 |
| [答：] |
接收机镜频频率上的规定信号电平与产生同样输出功率的调谐频率的（有用）信号电平之比.高性能的接收机需要有很高的镜频抑制比。 |
| [问：] |
能告诉我DDS发展趋势吗?其目前主要应用趋势是什么? |
| [答：] |
High frequency, high resolution and low power. It is mainly for the frequecy hopping application. Also it is widely used as an LO in many RF/IF applications. |
| [问：] |
能够采用两个DDS，采用不同的PLL倍频数，实现超宽带，比如1GH吗? |
| [答：] |
请注意目前最高速度的AD9858只适合于400MHz的频率输出，如果你需要更高带带宽，你可以和PLL配合使用，分别合成各自频段的信号频率。AD9956 integrate the DDS and PLL together and can output the frequency up to 2.7GHz. |
| [问：] |
你们的技术是不是主要应用在数字开关啊 |
| [答：] |
DDS is mainly for the frequency synthesizer.It can be used in where you need a variable frequency source. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
您好：请介绍此器件应用中典型电路。多谢 |
| [答：] |
Which part number do you need? Normally, you can find the typical circuits from its datasheet. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请教一下：要得到一个时域信号去掉某个频率范围后的新时域信号，用DDS技术的最方便和简单的硬件设计方案是什么？关键要求处理的延时越小越好，最好小于1微秒。谢谢！ |
| [答：] |
If you remove part of the spectrum in your input time domain signal, it works as a band notch filter. I don't think the DDS will be a good choice to make it work as a filter. If you care a lot about the filter delay, it depends on you application to select the right method to make your filter. Please contact with our China application support center for detail discussion about your application. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问：AD9857的Interpolating DAC Mode是将ad9857作为DAC器件使用吗? |
| [答：] |
Yes, the AD9857 works as an interpolating DAC in this model. |
| [问：] |
请问：如果生成非sin和cos波形，可用到dds 的那些功能实现？各位专家有什末推荐？ |
| [答：] |
Because the DDS only has the fixed look-up table, so only the sin/cos can be output directly. But if you still need other waveform, you can use the DDS as the frequency source and use the filter/comparator to generate the waveform as you need. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问:怎样减小DDS输出的噪音 |
| [答：] |
采用合适的输出滤波器与参考时钟，选用高性能的DDS产品，同时做好频率规划以减小杂散。减少杂散的关键是要让这些杂散频率落到你需要的带宽之外，预测这些杂散的关键，是要找出这些杂散在没有折叠回第一Nyquist区之前与基频之间的谐波关系。无论控制字或参考时钟频率如何变化，这些杂散和基频之间的谐波关系都会保持固定. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问ADI的DDS方案与MCU＋FPGA＋DAC的DDS方案相比，各有什么特点？ |
| [答：] |
ADI's DDS provide integrated solution with better performance, such as SFDR, higher output frequency up to 400MHz. FPGA+DAC can hardly achieve this performance. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问对于贵公司的AD9857进行IQ调制时，是否输入I、Q的数据率应当满足与参考时钟的某一个公式，还是只要工作在小于，参考时钟、工作模式（内插的数目、反sinc滤波等）所允许的最大I、Q速率之下就可以。我的理解是：工作模式选定，只要输入数据率小于，芯片进行内插滤波、调制所引起的最大时延就可以。谢谢 |
| [答：] |
For the modulation mode, the input data rate depends on the system clock, interpolation rate. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问贵公司在南京有没有办事处 |
| [答：] |
Sorry there is no ADI's office in Nanjing. But we have distributors there. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问目前的DDS一般能够工作到多高的频率？在这样的频率下，功耗达到多少？ |
| [答：] |
AD9858 can works at 1GHz with 400MHz output frequency, 2W power consumption. However, The power consumption is related other aspects. For our low power consumption parts: AD995x series, the power consumption is about 0.2W at 400MHz speed. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问用AD9854或AD9954产生AD6644的采样时钟对AD性能有没有多大影响？ |
| [答：] |
AD6644 is 14bit 65MSPS ADC.The clock jitter performance is very importance to such high speed and high resolution ADC.I recommend PLL+VCO to you to generate such kind of clock, rather than using DDS. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问用哪种方式可得到最佳效果的可编程改变的时钟频率 |
| [答：] |
It depends on your application, you can use PLL or DDS, or PLL+DDS parts from ADI. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
请问直接数字频率合成DDS和用DAC合成频率有什么优势？ |
| [答：] |
The most significant advantage is its fast frequency hopping capability. Because once the frequency control word is updated, dds will output a frequency. However if you want to use a DAC, you have give all the datas to generate a signal frequently. It should be noted that without DAC, there is no complete DDS. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
如果我希望用DDS产生一个固定频率的正弦信号，那么输出滤波器参数应该如何选择？还要定为40%采样频率吗？ |
| [答：] |
As long as the filter can select your expected frequency, that is enough, Bandpass filter is recommended in this kind of application. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
如何替代电视机高频头搜台 |
| [答：] |
This cannot be used to replace the TV tuner. It can only be used as part of the TV tuner. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
如今在通信领域软件无线电研究的如火如荼，然而困扰研究人员的问题就是前端的采集器件A/D和处理部分的核心器件DSP还不能达到人们的要求，恩能够否透漏一下贵公司现在这方面的研究成果，以及今后的在这方面研究重点？ |
| [答：] |
For the software radio, Adi provide VersaComm products (ADC, DAC, DDC, DUC), such as AD6652, AD6654, AD6633, AD6636,… For detailed information, please launch our website http://www.analog.com/en/subCat/0,2879,772%255F861%255F0%255F%255F0%255F,00.html. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
使用adi的芯片会不会大幅增加我们的成本？ |
| [答：] |
ADI can provide the best performance product with reasonable price. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
输出负载最大多少？ |
| [答：] |
Usually the output current is about 20mA. So the Rload can be several handred ohm (5V power supply). But we would recommend you using our parts according to the EVB. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
为什么ＡＤ的产品现货那么少．代理商只针对工厂客户做，贸易商怎么办．深圳是靠贸易为主，现在贸易商要购买ＡＤ的货比较麻烦，是否可以提供一家代理商只针对贸易商来做！ |
| [答：] |
Dropped |
| [问：] |
我们在使用AD9852发现，外界影响列入关开仪表对其有影响，什么原因呢？ |
| [答：] |
Perhaps this is due to the high frequency components mixed into AD9852's output and input. And the groundng of your design. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
我使用ad9835产生1MHz的输出．作为adf4001的参考频率,但是直接连接不能推动adf4001,如果中间接放大，则产生杂散，有没有更好的解决办法 |
| [答：] |
AD9835 can drive ADF4001. You need not to amplify it. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
我是一名学生,我想知道DDS产生波最高可以频率多高 |
| [答：] |
This will be decided by the chip you selected. For our part, AD9956 can output 2.7MHz clock. We have many kinds of DDS to cover a wide frequency range. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
我想问一下，能不能合成13.56MHz的频率，器件功耗多大？ |
| [答：] |
To answer your question, please let us know the reference clock. If the reference clock can be more than 34MHz, you can use AD9834 or AD995X to generate it. AD983x will be less than 100mW and AD995X will be almost 200mW. Please refer to their datasheet for details. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
我想在DDS后面通过PLL来降低输出信号的相噪。请问是否有相关资料介绍如何考虑PLL的传输特性以达到较好效果？ |
| [答：] |
Normally, the phase noise can be improved by the frequency division. So, it will be difficult to improve the DDS output by using PLL. Can you provide any details, then we can discuss the solution. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
我在用ADS9856时，离散的数字干扰对DDS的输出频率稳定度影响很大，什么方法可以有效改善？ |
| [答：] |
Maybe you mention AD9856 in the question. For the digital influence the DDS quality, please pay attention to the layout, especially the digital ground and analgo ground and the power decoupling. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
相位累加器的切断如何影响到输出正弦波的噪音?如何选择参数来降低正弦波的波纹? |
| [答：] |
Please refer to page 19 to 24 of the presentation. One way is to select the suitale freqency for the output. You can also use the filter to improve it. This can be found from the article "DDS design". For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
一般情况下三次谐波具体的能量较高，为什么二次谐波也具有较大的能量？ |
| [答：] |
In fact, this will be decided by the system clock frequency and the output frequency. If the 2nd, 3rd harmonic is in the 1st Nyquist zone, you are right. But, if not, this will be re-considered. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
用DDS技术产生线性调频信号,其中心频率与带宽最大能够达到多少？ |
| [答：] |
The center frequency cannot be higher than 40% system clock. The bandwidth will be decided by your system requirement, remember there is SINC in the output. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
用于S波段，目前各项性能指标能达到何程度？ |
| [答：] |
Do you mean DDS used in S-band (1.55GHz to 3.9GHz)? We have AD9956 can be used, but cannnot cover the whole S-band. So, you can use it by combine DDS and PLL. Our PLL is ADF41XX. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
在DDS+PLL中,用DDS作基准时,PLL倍频次数最高能达到多少? |
| [答：] |
This is decided by the PLL and the clock quality requirement. You know, the DDS's spurs will be output with the gain of 20logN. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
在DDS输出端实现幅度调制,需要增加什么器件? |
| [答：] |
For the AM by using DDS, you can implement in two ways: adjust the R_set pin of the DDS or use two DDS to do that. For theh 1st one, you have to select a digital controlled variable resistor, ADI has this kind of part. For the 2nd way, we used the current output and one resistor to convert it into voltage. We have this kind of article, please contact us. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
在高频率端，使用PLL还是DDS比较妥？ |
| [答：] |
What do you mean the high frequency? Would you please let us know the output frequency requirement and the reference clock frequency, thus we can help you on this question. Also, please contact us via 800 810 1742 or china.support@analgo.com. |
| [问：] |
在实际使用中,请问利用带内部精密比较电压的芯片好还是不带的好呢? |
| [答：] |
Maybe you indicate the comparator used in the DDS. Normally, if the integated comparator can meet your requirement, use it, and the solution will be simple and easy. If the comparator inside cannot meet your requirement, please use external one. For further technical support contact us via 800 810 1742 or china.support@analog.com, please. |
| [问：] |
在我的工作中对频率合成的理解就是通过CPU对PLL环路控制,不知DDS有哪些优越性? |
| [答：] |
There are two kinds of clock synthesizer technology: PLL and DDS. For PLL, it can generate higher frequency than the reference clock, but lower transaction and lower frequency resolution. For DDS, it can generate output within 40% of the system clock, but higher transition time and higher frequency resolution. For details, contact us via 800 810 1742 or china.support@analog.com. |
| [问：] |
专家,您好.我们现在的项目用到AD9854,遇到些问题,向您请教:AD9854的控制字写的都是正确的,但是出来的波形频率(signal tone)在控制字所控制的输出的波形的周围范围波动,而且它的波形的包络看起来像一个和REFCLK的频率一样的波形.请问专家,这种现象有可能是哪些原因引起的? |
| [答：] |
This seems to be that the analog output has been modualted bythe reference clock. Is it possible for you to let us know the frequency of your reference clock and the output clock? Thus we can solve the problem. Feel free to contact us via 800 810 1742 or china.support@analog.com. |
| [问：] |
专家你认为DDS输出滤波器,数字和模拟滤波器那一种的效果会更好? |
| [答：] |
For the DDS output, the analog filter is needed. You know normally, there will be no digital filter after the DDS, because DDS's output is analog. |
